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ISL21007
Data Sheet December 13, 2007 FN6326.7
Precision, Low Noise FGATMVoltage References
The ISL21007 FGATM voltage references are extremely low power, high precision, and low noise voltage references fabricated on Intersil's proprietary Floating Gate Analog technology. The ISL21007 features very low noise (4.5VP-P for 0.1Hz to 10Hz) and very low operating current (150A, Max). In addition, the ISL21007 family features guaranteed initial accuracy as low as 0.5mV. This combination of high initial accuracy, low drift, and low output noise performance of the ISL21007 enables versatile high performance control and data acquisition applications with low power consumption.
Features
* Reference Output Voltage . . . . . .1.250V, 2.048V, 2.500V, 3.000V * Initial Accuracy . . . . . . . . . . . . . . . . . . . . 0.5mV (B grade) * Input Voltage Range ISL21007-12, 20, 25. . . . . . . . . . . . . . . . . . . . .2.7V to 5.5V ISL21007-30. . . . . . . . . . . . . . . . . . . . . . . . . . 3.2V to 5.5V * Low Output Voltage Noise . . . . .4.5VP-P (0.1Hz to 10Hz) * Supply Current . . . . . . . . . . . . . . . . . . . . . . . .150A (Max) * Temperature Coefficient . . . . . . . . . . . . 3ppm/C (B grade) * Operating Temperature Range. . . . . . . . . -40C to +125C * Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld SOIC * Pb-Free (RoHS Compliant)
Available Options
VOUT OPTION (V) 1.250 1.250 1.250 2.048 2.048 2.048 2.500 2.500 2.500 3.000 3.000 3.000 INITIAL ACCURACY (mV) 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 0.5 1.0 2.0 TEMPCO. (ppm/C) 3 5 10 3 5 10 3 5 10 3 5 10
Applications
* High Resolution A/Ds and D/As * Digital Meters * Bar Code Scanners * Basestations * Battery Management/Monitoring * Industrial/Instrumentation Equipment
PART NUMBER ISL21007BFB812Z ISL21007CFB812Z ISL21007DFB812Z ISL21007BFB820Z ISL21007CFB820Z ISL21007DFB820Z ISL21007BFB825Z ISL21007CFB825Z ISL21007DFB825Z ISL21007BFB830Z ISL21007CFB830Z ISL21007DFB830Z
Pinout
ISL21007 (8 LD SOIC) TOP VIEW GND or NC 1 VIN 2 DNC 3 GND 4 8 DNC 7 DNC 6 VOUT 5 TRIM
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. FGA is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL21007 Ordering Information
PART NUMBER (Notes 1, 2) ISL21007BFB812Z ISL21007CFB812Z ISL21007DFB812Z ISL21007BFB820Z ISL21007CFB820Z ISL21007DFB820Z ISL21007BFB825Z ISL21007CFB825Z ISL21007DFB825Z ISL21007BFB830Z ISL21007CFB830Z ISL21007DFB830Z NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. PART MARKING 21007BF Z12 21007CF Z12 21007DF Z12 21007BF Z20 21007CF Z20 21007DF Z20 21007BF Z25 21007CF Z25 21007DF Z25 21007BF Z30 21007CF Z30 21007DF Z30 VOUT OPTION (V) 1.250 1.250 1.250 2.048 2.048 2.048 2.500 2.500 2.500 3.000 3.000 3.000 GRADE 0.5mV, 3ppm/C 1.0mV, 5ppm/C 2.0mV, 10ppm/C 0.5mV, 3ppm/C 1.0mV, 5ppm/C 2.0mV, 10ppm/C 0.5mV, 3ppm/C 1.0mV, 5ppm/C 2.0mV, 10ppm/C 0.5mV, 3ppm/C 1.0mV, 5ppm/C 2.0mV, 10ppm/C TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC PKG. DWG. # M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15 M8.15
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FN6326.7 December 13, 2007
ISL21007 Pin Descriptions
PIN NUMBER 1 2 4 5 6 3, 7, 8 PIN NAME GND or NC VIN GND TRIM VOUT DNC Ground or No Connection Power Supply Input Connection Ground Allows user trim VOUT 2.5% Voltage Reference Output Connection Do Not Connect; Internal Connection - Must Be Left Floating DESCRIPTION
Typical Application Circuit
1 GND +3V C1 10F 2 VIN 3 NC 4 GND NC 8 NC 7 VOUT 6 TRIM 5
ISL21007-12, 20, 25, 30 SPI BUS X79000 1 SCK 2 A0 3 A1 4 A2 5 SI 6 SO 7 RDY 8 UP 9 DOWN 10 OE CS 20 CLR 19 VCC 18 VH 17 VL 16 VREF 15 VSS 14 VOUT 13 VBUF 12 VFB 11 LOW NOISE DAC OUTPUT C1 0.001F
FIGURE 1. TYPICAL APPLICATION PRECISION 12-BIT SUBRANGING DAC
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FN6326.7 December 13, 2007
ISL21007
Absolute Voltage Ratings
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to +6.5V Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . . -0.5V to VOUT + 1 Voltage on "DNC" pins . . . . No connections permitted to these pins. ESD Rating Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . .6kV Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600V Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.12 Continuous Power Dissipation (Note 3) . . . . . . . . . . . . . TA = +70C 8 Ld SOIC derate 5.88mW/C above +70C . . . . . . . . . . . . 471mW Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . .-40C to +125C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Common Electrical Specifications (ISL21007-12, -20, -25, -30) TA = -40C to +125C, unless otherwise specified.
PARAMETER VOA DESCRIPTION VOUT Accuracy @ TA = +25C ISL21007B ISL21007C ISL21007D TC VOUT Output Voltage Temperature Coefficient (Note 4) ISL21007B ISL21007C ISL21007D IIN Supply Current Trim Range tR Turn-on Settling Time Ripple Rejection eN VN Output Voltage Noise Broadband Voltage Noise Noise Density VOUT = 0.1% f = 10kHz 0.1Hz f 10Hz 10Hz f 1kHz f = 1kHz 2.0 75 2.5 120 60 4.5 2.2 60 CONDITIONS MIN -0.5 -1.0 -2.0 TYP MAX +0.5 +1.0 +2.0 3 5 10 150 UNIT mV mV mV ppm/C ppm/C ppm/C A % s dB VP-P VRMS nV/Hz
Electrical Specifications (ISL21007-12, VOUT = 1.250V) VIN = 3.0V, TA = -40C to +125C, unless otherwise specified.
PARAMETER VIN VOUT VOUT /VIN VOUT/IOUT DESCRIPTION Input Voltage Range Output Voltage Line Regulation Load Regulation 2.7V < VIN < 5.5V Sourcing: 0mA IOUT 7mA Sinking: -7mA IOUT 0mA ISC VOUT/TA VOUT/t Short Circuit Current Thermal Hysteresis (Note 5) Long Term Stability (Note 6) TA = +25C, VOUT tied to GND TA = +165C TA = +25C CONDITIONS MIN 2.7 1.250 100 10 20 40 50 100 700 100 150 TYP MAX 5.5 UNIT V V V/V V/mA V/mA mA ppm ppm
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FN6326.7 December 13, 2007
ISL21007
Electrical Specifications (ISL21007-20, VOUT = 2.048V) VIN = 3.0V, TA = -40C to +125C, unless otherwise specified.
PARAMETER VIN VOUT VOUT /VIN VOUT/IOUT DESCRIPTION Input Voltage Range Output Voltage Line Regulation Load Regulation 2.7V < VIN < 5.5V Sourcing: 0mA IOUT 7mA Sinking: -7mA IOUT 0mA ISC VOUT/TA VOUT/t Short Circuit Current Thermal Hysteresis (Note 5) Long Term Stability (Note 6) TA = +25C, VOUT tied to GND TA = +165C TA = +25C CONDITIONS MIN 2.7 2.048 50 10 20 50 50 75 200 100 150 TYP MAX 5.5 UNIT V V V/V V/mA V/mA mA ppm ppm
Electrical Specifications (ISL21007-25, VOUT = 2.500V) VIN = 3.0V, TA = -40C to +125C, unless otherwise specified
PARAMETER VIN VOUT VOUT /VIN VOUT/IOUT DESCRIPTION Input Voltage Range Output Voltage Line Regulation Load Regulation 2.7V < VIN < 5.5V Sourcing: 0mA IOUT 5mA Sinking: -5mA IOUT 0mA ISC VOUT/TA VOUT/t Short Circuit Current Thermal Hysteresis (Note 5) Long Term Stability (Note 6) TA = +25C, VOUT tied to GND TA = +165C TA = +25C CONDITIONS MIN 2.7 2.500 50 10 20 50 50 50 200 100 150 TYP MAX 5.5 UNIT V V V/V V/mA V/mA mA ppm ppm
Electrical Specifications (ISL21007-30, VOUT = 3.000V) VIN = 5.0V, TA = -40C to +125C, unless otherwise specified
PARAMETER VIN VOUT VOUT /VIN VOUT/IOUT DESCRIPTION Input Voltage Range Output Voltage Line Regulation Load Regulation 3.2V < VIN < 5.5V Sourcing: 0mA IOUT 7mA Sinking: -7mA IOUT 0mA ISC VOUT/TA VOUT/t Short Circuit Current Thermal Hysteresis (Note 5) Long Term Stability (Note 6) TA = +25C, VOUT tied to GND TA = +165C TA = +25C CONDITIONS MIN 3.2 3.000 50 10 20 50 50 50 200 100 150 TYP MAX 5.5 UNIT V V V/V V/mA V/mA mA ppm ppm
4. Over the specified temperature range. Temperature coefficient is measured by the box method whereby the change in VOUT is divided by the temperature range; in this case, -40C to +125C = +165C. 5. Thermal Hysteresis is the change of VOUT measured at TA = +25C after temperature cycling over a specified range, TA. VOUT is read initially at TA = +25C for the device under test. The device is temperature cycled and a second VOUT measurement is taken at +25C. The difference between the initial VOUT reading and the second VOUT reading is then expressed in ppm. For TA = +165C, the device under test is cycled from +25C to +125C to -40C to +25C. 6. Long term drift is logarithmic in nature and diminishes over time. Drift after the first 1000 hours will be approximately 10ppm/(1kHrs)
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-12) (REXT = 100k)
120 UNIT 3 100 80 IIN (A) IIN (A) UNIT 2 60 40 20 0 2.5 UNIT 1 90 85 80 75 70 65 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 60 2.5 3.0 3.5 -40C +25C +125C 95
4.0 VIN (V)
4.5
5.0
5.5
FIGURE 2. IIN vs VIN (3 UNITS)
FIGURE 3. IIN vs VIN OVER TEMPERATURE
VOUT (V) (NORMALIZED TO 1.250V AT VIN = 3.0V)
1.25015 VO (V) (NORMALIZED TO VIN = 3.0V) 1.25010 UNIT 3 1.25005 1.25000 UNIT 2 1.24995 1.24990 UNIT 1 1.24985 1.24980 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5
150 100 50 0 -50 -100 -150 -200 -250 -300 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 +25C -40C +125C
FIGURE 4. LINE REGULATION (3 UNITS)
FIGURE 5. LINE REGULATION OVER TEMPERATURE
0.15 +25C 0.10 VOUT (mV) 0.05 VOUT (V) 0.00 -0.05 -0.10 -0.15 -40C +125C
1.25010 1.25005 1.25000 1.24995 1.24990 1.24985 1.24980 -7 -6 -5 -4 SINKING -3 -2 -1 0 1 2 3 OUTPUT CURRENT (mA) 4567 SOURCING 1.24975 -40 -20 0 20 40 60 80 100 120 140 UNIT 3 UNIT 2 UNIT 1
TEMPERATURE (C)
FIGURE 6. LOAD REGULATION OVER TEMPERATURE
FIGURE 7. VOUT vs TEMPERATURE (3 UNITS)
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-12) (REXT = 100k)
(Continued)
X: 200mV/DIV Y: 10s/DIV 0 -20 PSRR (dB) -40 -60 1F LOAD -80 -100 1.00E+00 1nF LOAD NO LOAD 1.00E+02 1.00E+04 1.00E+0 VIN = -0.3V 10nF LOAD 100nF LOAD VIN = +0.3V
FREQUENCY (Hz)
FIGURE 8. PSRR vs CAPACITIVE LOADS
FIGURE 9. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
X: 200mV/DIV Y: 10s/DIV
X: 20s/DIV Y: 1V/DIV
VIN = +0.3V
VIN
VIN = -0.3V
VOUT = 1.25V
FIGURE 10. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
FIGURE 11. TURN-ON TIME
GAIN IS x1000, NOISE IS 4.5VP-P 140 120 100 ZOUT () 80 60 40 20 0 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1nF 10nF 100nF NO LOAD
FREQUENCY (Hz)
FIGURE 12. ZOUT vs FREQUENCY
2mV/DIV
FIGURE 13. VOUT NOISE, 0.1Hz TO 10Hz
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-12) (REXT = 100k)
NO OUTPUT CAPACITANCE X: 50s/DIV Y: 1V/DIV
(Continued)
+7mA
-7mA
FIGURE 14. LOAD TRANSIENT RESPONSE
Typical Performance Curves (ISL21007-20) (REXT = 100k)
95 90 85 IIN (A) IIN (uA) 80 75 70 65 2.7 UNIT 3 3.1 3.5 3.9 4.3 4.7 5.1 5.5 UNIT 1 UNIT 2 95 90 85 80 75 70 65 60 55 50 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 +25C -40C +125C
VIN (V)
VIN (V)
FIGURE 15. IIN vs VIN (3 UNITS)
FIGURE 16. IIN vs VIN OVER TEMPERATURE
VOUT (V) NORMALIZED TO 2.048V AT VIN = 3.0V
2.04815 UNIT 2 2.04810 2.04805 UNIT 1 2.04800 2.04795 2.04790 2.5 UNIT 3
VOUT (V) (NORMALIZED TO 2.048V AT VIN = 3V)
2.04815 -40C 2.04810 +125C 2.04805 +25C 2.04800
3.0
3.5
4.0 VIN(V)
4.5
5.0
5.5
2.04795
2.5
3.0
3.5
4.0 VIN(V)
4.5
5.0
5.5
FIGURE 17. LINE REGULATION (3 UNITS)
FIGURE 18. LINE REGULATION OVER TEMPERATURE
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-20) (REXT = 100k)
VOUT(V) NORMALIZED TO 2.048V AT +25C VOUT (mV) NORMALIZED TO 0mA 1.6 1.2 0.0 0.4 0.0 -0.4 -0.8 -1.2 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 +25C -40C +125C
(Continued)
2.0496 2.0492 2.0488 2.0484 2.0480 2.0476 UNIT 3 2.0472 -40 -25 -10 5 20 35 50 65 80 95 110 125 UNIT 2 UNIT 1
SINKING
OUTPUT CURRENT (mA)
SOURCING
TEMPERATURE (C)
FIGURE 19. LOAD REGULATION OVER TEMPERATURE
FIGURE 20. VOUT vs TEMPERATURE (3 UNITS)
X: 200mV/DIV Y: 10s/DIV 0 10nF LOAD -20 PSRR (dB) -40 -60 -80 -100 1.0E+01 1F LOAD VIN = -0.3V 100nF LOAD VIN = +0.3V
NO LOAD
1.0E+03 FREQUENCY (Hz)
1.0E+05
FIGURE 21. PSRR vs CAPACITIVE LOADS
FIGURE 22. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
X: 200mV/DIV Y: 10s/DIV
X: 100s/DIV Y: 2V/DIV
VIN = +0.3V VIN
VOUT = 2.048V VIN = -0.3V
FIGURE 23. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
FIGURE 24. TURN-ON TIME
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-20) (REXT = 100k)
(Continued)
GAIN IS x1000, NOISE IS 4.5VP-P 140 120 100 ZOUT () 80 60 40 20 0 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1nF 10nF 100nF 2mV/DIV FREQUENCY (Hz) NO LOAD
FIGURE 25. ZOUT VS FREQUENCY
FIGURE 26. VOUT NOISE, 0.1Hz TO 10Hz
X: 20s/DIV Y: 200mV/DIV +7mA
X: 20s/DIV Y: 200mV/DIV
+7mA
-7mA
-7mA
FIGURE 27. LOAD TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
FIGURE 28. LOAD TRANSIENT RESPONSE, NO CAPACITIVE LOAD
Typical Performance Curves (ISL21007-25) (REXT = 100k)
120 UNIT 3 100 80 IIN (A) 60 40 70 20 0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 6.0 65 60 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 UNIT 1 UNIT 2 IIN (A) 100 95 90 85 80 75 +25C -40C +125C
FIGURE 29. IIN vs VIN (3 UNITS)
FIGURE 30. IIN vs VIN OVER TEMPERATURE
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-25) (REXT = 100k)
VOUT (V) (NORMALIZED TO 2.500V AT VIN = 3V) 2.5002 2.5001 2.5000 UNIT 2 2.4999 2.4998 2.4997 2.4996 2.5 UNIT 3 UNIT 1 VO (V) (NORMALIZED TO VIN = 3.0V)
(Continued)
100 50 0 -50
-100 -150 -200 -250 -300 -350 -400 2.5
+25C +125C
-40C
3.0
3.5
4.0 VIN (V)
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
FIGURE 31. LINE REGULATION (3 UNITS)
FIGURE 32. LINE REGULATION OVER TEMPERATURE
0.6 0.4 0.2 VOUT (mV) 0 -0.2 -0.4 -0.6 -0.8 -1.0 -7 -6 -5 -4 SINKING +25C
2.5003
+125C -40C
VOUT (V)
2.5002 2.5001 2.5000 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994
UNIT 2
UNIT 1
UNIT 3 -20 0 20 40 60 80 100 120 140
-3 -2 -1
0
1
2
3
4
5
6
7
2.4993 -40
OUTPUT CURRENT (mA)
SOURCING
TEMPERATURE (C)
FIGURE 33. LOAD REGULATION OVER TEMPERATURE
FIGURE 34. VOUT vs TEMPERATURE (3 UNITS)
X: 200mV/DIV Y: 10s/DIV 10 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -90 -100 1.E+00 1.E+02 1.E+04 1.E+06 VIN = -0.3V
NO LOAD 1nF 10nF 100nF 1F
VIN = +0.3V
FREQUENCY (Hz)
FIGURE 35. PSRR vs CAPACITIVE LOADS
FIGURE 36. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-25) (REXT = 100k)
X: 200mV/DIV Y: 10s/DIV
(Continued)
X: 20s/DIV Y: 1V/DIV
VIN = +0.3V VIN
VIN = -0.3V
VOUT = 2.5V
FIGURE 37. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
FIGURE 38. TURN-ON TIME
GAIN IS x1000, NOISE IS 4.5VP-P 140 120 100 ZOUT () 80 60 40 20 0 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1nF 10nF 100nF NO LOAD
FREQUENCY (Hz)
2mV/DIV
FIGURE 39. ZOUT vs FREQUENCY
FIGURE 40. VOUT NOISE, 0.1Hz TO 10Hz
NO OUTPUT CAPACITANCE X: 50s/DIV Y: 500mV/DIV +5mA
-5mA
FIGURE 41. LOAD TRANSIENT RESPONSE
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-30) (REXT = 100k)
120 UNIT 2 100 80 IIN (A) 60 40 20 0 3.2 3.7 4.2 VIN (V) 4.7 5.2 UNIT 1 IIN (A) UNIT 3 100 80 60 40 20 0 3.2 3.7 4.2 VIN (V) 4.7 5.2 +25C -40C 120 +125C
FIGURE 42. IIN vs VIN (3 UNITS)
FIGURE 43. IIN vs VIN OVER TEMPERATURE
VOUT(V) NORMALIZED TO 3.0V AT 5.0VIN
UNIT 1 UNIT 2 UNIT 3
VOUT (V) NORMALIZED TO 3.0V AT 5.0VIN
3.0005 2.9995 2.9985 2.9975 2.9965 2.9955 3.2
3.001 3.000 2.999 2.998 2.997 2.996 2.995 2.994 3.2 3.6 4.0 4.4 VIN (V) 4.8 5.2 5.6 -40C +25C +125C
3.6
4.0
4.4 VIN (V)
4.8
5.2
5.6
FIGURE 44. LINE REGULATION (3 UNITS)
FIGURE 45. LINE REGULATION OVER TEMPERATURE
VOUT (mV) NORMALIZED TO 0mA
0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -7 -6 -5 -4 -3 -2 -1 SINKING 0 1 2 3 4 5 6 7 +125C +25C -40C
VOUT (V) NORMALIZED TO 3.0V AT +25C
3.0006 3.0004 3.0002 3.0000 2.9998 2.9996 2.9994 2.9992 2.9990 -40 -25 -10 5 20 35 50 65 80 95 110 125 UNIT 1 UNIT 2 UNIT 3
LOAD (mA)
SOURCING
TEMPERATURE (C)
FIGURE 46. LOAD REGULATION OVER TEMPERATURE
FIGURE 47. VOUT vs TEMPERATURE (3 UNITS)
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-30) (REXT = 100k)
(Continued)
X: 200mV/DIV Y: 10s/DIV 10 0 VIN (DC) = 5.0V -10 VIN (AC) = 50mVP-P -20 -30 -40 -50 -60 -70 -80 -90 -100 1.E+00 1.E+02 NO LOAD 1nF 10nF 100nF 1F VIN = +0.5V
PSRR (dB)
VIN = -0.5V 1.E+04 1.E+06
FREQUENCY (Hz)
FIGURE 48. PSRR vs CAPACITIVE LOADS
FIGURE 49. LINE TRANSIENT RESPONSE, NO CAPACITIVE LOAD
X: 200mV/DIV Y: 10s/DIV VIN = 5.0V VIN = +0.5V VOUT = 3.0V
VIN = -0.5V
1V/DIV
20s/DIV
FIGURE 50. LINE TRANSIENT RESPONSE, 0.001F LOAD CAPACITANCE
FIGURE 51. TURN-ON TIME
GAIN IS x1000, NOISE IS 4.5VP-P 140 120 100 ZOUT () 80 60 40 20 0 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1nF 10nF 100nF NO LOAD
FREQUENCY (Hz)
FIGURE 52. ZOUT vs FREQUENCY
2mV/DIV
FIGURE 53. VOUT NOISE, 0.1Hz TO 10Hz
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FN6326.7 December 13, 2007
ISL21007 Typical Performance Curves (ISL21007-30) (REXT = 100k)
(Continued)
+7mA 200mV/DIV
-7mA
100s/DIV
FIGURE 54. LOAD TRANSIENT RESPONSE
Applications Information
FGA Technology
The ISL21007 voltage reference uses floating gate technology to create references with very low drift and supply current. Essentially, the charge stored on a floating gate cell is set precisely in manufacturing. The reference voltage output itself is a buffered version of the floating gate voltage. The resulting reference device has excellent characteristics which are unique in the industry: very low temperature drift, high initial accuracy, and almost zero supply current. Also, the reference voltage itself is not limited by voltage bandgaps or zener settings, so a wide range of reference voltages can be programmed (standard voltage settings are provided, but customer-specific voltages are available). The process used for these reference devices is a floating gate CMOS process, and the amplifier circuitry uses CMOS transistors for amplifier and output transistor circuitry. While providing excellent accuracy, there are limitations in output noise level and load regulation due to the MOS device characteristics. These limitations are addressed with circuit techniques discussed in other sections.
Board Mounting Considerations
For applications requiring the highest accuracy, board mounting location should be reviewed. The device uses a plastic SOIC package, which will subject the die to mild stresses when the PC board is heated and cooled and slightly change its shape. Placing the device in areas subject to slight twisting can cause degradation of the accuracy of the reference voltage due to these die stresses. It is normally best to place the device near the edge of a board, or the shortest side, as the axis of bending is most limited at that location. Mounting the device in a cutout also minimizes flex. Obviously, mounting the device on flexprint or extremely thin PC material will likewise cause loss of reference accuracy.
Noise Performance and Reduction
The output noise voltage in a 0.1Hz to 10Hz bandwidth is typically 4.5VP-P. The noise measurement is made with a bandpass filter made of a 1 pole high-pass filter with a corner frequency at 0.1Hz and a 2-pole low-pass filter with a corner frequency at 12.6Hz to create a filter with a 9.9Hz bandwidth. Noise in the 10kHz to 1MHz bandwidth is approximately 40VP-P with no capacitance on the output. This noise measurement is made with a 2 decade bandpass filter made of a 1 pole high-pass filter with a corner frequency at 1/10 of the center frequency and 1-pole low-pass filter with a corner frequency at 10 times the center frequency. Load capacitance up to 1000pF can be added but will result in only marginal improvements in output noise and transient response. The output stage of the ISL21007 is not designed to drive heavily capacitive loads, so for load capacitances above 0.001F, the noise reduction network shown in Figure 55 is recommended. This network reduces noise significantly over the full bandwidth. Noise is reduced to less than 20VP-P from 1Hz to 1MHz using this network with a 0.01F capacitor and a 2k resistor in series with a 10F capacitor. Also, transient response is improved with higher value output capacitor. The 0.01F value can be increased for better load transient response with little sacrifice in output stability.
FN6326.7 December 13, 2007
Micropower Operation
The ISL21007 consumes extremely low supply current due to the proprietary FGA technology. Low noise performance is achieved using optimized biasing techniques. Supply current is typically 75A and noise is 4.5VP-P benefitting precision, low noise portable applications such as handheld meters and instruments. Data Converters in particular can utilize the ISL21007 as an external voltage reference. Low power DAC and ADC circuits will realize maximum resolution with lowest noise.
15
ISL21007
Turn-On Time
The ISL21007 devices have low supply current and thus the time to bias up internal circuitry to final values will be longer than with higher power references. Normal turn-on time is typically 120s. This is shown in Figure 10. Circuit design must take this into account when looking at power-up delays or sequencing.
Output Voltage Adjustment
The output voltage can be adjusted up or down by 2.5% by placing a potentiometer from VOUT to ground, and connecting the wiper to the TRIM pin. The TRIM input is high impedance, so no series resistance is needed. The resistor in the potentiometer should be a low tempco (<50ppm/C) and the resulting voltage divider should have very low tempco <5ppm/C. A digital potentiometer such as the ISL95810 provides a low tempco resistance and excellent resistor and tempco matching for trim applications. See Figure 58 and TB473 for further information.
VIN = 5.0V 10F 0.1F VIN VO ISL21007 GND 0.01F 10F 2k
Temperature Coefficient
The limits stated for temperature coefficient (tempco) are governed by the method of measurement. The overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures, take the total variation, (VHIGH - VLOW), and divide by the temperature extremes of measurement (THIGH - TLOW). The result is divided by the nominal reference voltage (at T = +25C) and multiplied by 106 to yield ppm/C. This is the "Box" method for specifying temperature coefficient.
FIGURE 55. HANDLING HIGH LOAD CAPACITANCE
Typical Application Circuits
VIN = +5.0V R = 200 2N2905
VIN ISL21007 VOUT VOUT = 2.500V GND 2.5V/50mA 0.001F
FIGURE 56. PRECISION 2.500V 50mA REFERENCE
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FN6326.7 December 13, 2007
ISL21007 Typical Application Circuits (Continued)
+2.7 TO 5.5V 0.1F 10F
VIN VOUT ISL21007-25 VOUT = 2.500V GND
0.001F VCC RH + EL8178 - RL VOUT (BUFFERED) VOUT (UNBUFFERED)
X9119 SDA 2-WIRE BUS SCL VSS
FIGURE 57. 2.500V FULL SCALE LOW-DRIFT, LOW NOISE, 10-BIT ADJUSTABLE VOLTAGE SOURCE
+2.7 TO 5.5V 0.1F 10F
VIN VOUT ISL21007-12 GND + -
EL8178 VOUT SENSE LOAD
FIGURE 58. KELVIN SENSED LOAD
+2.7 TO 5.5V 0.1F
10F
VIN VOUT ISL21007-12 TRIM GND
2.5V 2.5%
VCC I2C BUS SDA SCL ISL95810 VSS
RH
RL
FIGURE 59. OUTPUT ADJUSTMENT USING THE TRIM PIN
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FN6326.7 December 13, 2007
ISL21007 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN6326.7 December 13, 2007

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